Certifying modular PLDs with the Universal Verification Methodology
Whilst they present a powerful tool, the use of PLDs in critical systems faces a number of on-going challenges that a leading to increased cost and timescales. Key issues include increased design size & complexity, increased certification requirements, and evolution of the underlying technology.
This talk will present a number of improvements in the approach to verifying PLDs that target these issues, with a particular emphasis on the use constrained random testing within a Universal Verification Methodology (UVM) framework.
Speaker
Richard Harriss
Lead PLD Engineer, BAE Systems
Richard Harriss is an experienced FPGA design engineer and systems engineer specialising in high performance imaging and image processing systems for both space and aerospace applications. Educated to undergraduate level at Oxford University, Richard also holds a PhD in optoelectronics.
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