Edge Avionics with Digital Security by Design

Paul Caseley

Fellow, Defence Science and Technology Laboratory (Dstl)

This presentation will discuss and elaborate the purpose and strategic thinking of the MOD/Dstl Edge Avionics with Digital Security by Design technology.

Background:

Secure by Design is the overriding strategic priority of MOD’s Cyber Resilience Strategy for Defence and will be likely in MOD contracts and updated Defence Standards.

As part of Wave 3 Industrial Strategy Challenge, UK Research and Innovation (UKRI, Innovate UK) the Digital Security by Design (DSbD) project delivered secure silicon in the form of a Capability Hardware Enhanced RISC Instructions (CHERI) based Technology Platform Prototype (TPP) called Morello. The Morello TPP is a multicore evaluation board with supporting system software. It is estimated CHERI blocks up to 70% of memory vulnerabilities in the software stack in the Morello hardware by enforcing a formally verified fine grained memory control. The new capability is a potential step change in reducing the attack surface below the software stack.

Integration of priority and technology:

The Edge Avionics with Digital Security by Design concept arose out the opportunity to design a defence related project/demonstrator to exploit the new secure silicon processers using CHERI technology.

Dstl, with industrial partners, is developing a demonstration Avionics architecture using Morello and enhanced aerospace tools and data concentrators to produce an experimental Edge Avionics architecture. This presentation will overview the underpinning technologies; how they are being integrated, development of adapting legacy software, development of new tool technologies and new innovations that generally benefit the high integrity ecosystem.

Depending on how the project has progressed early results from the integration and research program may be shared.

About Paul Caseley

Paul Caseley OBE, works for the UK Ministry of Defence (MOD) Defence Science and Technologies Laboratory (Dstl). He is a Dstl Fellow and is one of MOD’s leading advisors for science and technology research and engineering of software dependent mission, security and safety related systems. His recent research activities are in areas of implementation of autonomous functions, cyber impacts on safety, and system risk (cyber, security and safety). Paul’s publically accessible work includes editor and technical lead for MOD Defence Standards 00-056 (Issue 7 Feb 2017) and 00-055 (Issue 4 Apr 2016).

Paul also works extensively within the UK and International software, security and safety communities - academic and industrial. Paul is a Chartered Engineer and is a Fellow of the IET, BCS and SaRs. He is also a Senior Member and is a Certified Professional in Safety Critical Systems with the Australian Computer Society.

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