Multi-core Interference Tuning and Analysis
Research Postgraduate, Imperial College Department of Computing
Multicore architectures can be leveraged to allow independent processes to run in parallel. However, due to resources shared across cores, such as caches and buses, such processes may observably interfere with one another. In particular, this interference can affect important non-functional properties of a program, such as the execution time. Formally reasoning about such interference is difficult due to the complexity and proprietary nature of modern processors; additionally, interference developed for one architecture may not be effective on a different architecture. To address these difficulties, we propose an auto-tuning framework that optimises interference that causes single-core program slowdown in a multicore environment. Quantifying interference has many potential applications including both hard and soft real-time systems; optimising the placement of processes on multiple cores; reverse-engineering architectural features; identifying counterfeit processors.
Our framework creates interference by launching enemy processes; a parameterised stressing program. While the enemy process template is written manually, automated tuning techniques can be used to search for effective parameters. We explore four common searching techniques: random search, hillclimbing, simulated annealing and Bayesian optimisation with the aim of finding the enemy processes parameters causing the highest interference. Our methods are developed to be portable across a variety of architectures such that enemy processes can be tuned to target unique micro-architectural features